This invention relates to a multiplying digital-to-analogue converter circuit arrangement comprising a current mirror arrangement constructed to generate currents -2.sup.-1 I.sub.1,-2.sup.-2 I.sub.1, . . . , -2.sup.-n I.sub.1 at first, second, . . . nth outputs respectively thereof in response to the application of a current J.sub.1 to an input thereof, where I.sub.1 is in a predetermined ratio to J.sub.1, and a respective controllable switch coupling each said output to an output of the converter circuit arrangement, control inputs of said switches collectively constituting the digital signal input of said converter circuit arrangement.
Known such converter circuit arrangements are disclosed in, for example, IBM Technical Disclosure Bulletin Vol. 24, No. 5, (October 1981) at pages 2342-2344, and in JP-A-61-2427. Each of these known converter arrangements generates a current at its output when a current is applied to the current mirror input and at least one of the switches is closed, the output current being proportional to both the mirror input current and the number represented by the digital code constituted by the configuration of closed and open switches prevailing at the relevant time. The input currents to the current mirror arrangements of these known converters must always have a specific polarity if the mirror arrangements are to operate correctly, and it will be evident moreover that the output currents of these known converters always have a specific polarity too, whatever the value of the mirror input current and/or the configuration of open and closed switches actually is.
In some possible applications for multiplying digital-to-analogue converts there is a requirement that the converter be capable of operating with analogue input signal currents of either polarity and generating output currents having polarity which is governed by that of the input signal current regardless of what the particular value of the converter digital input signal is at the relevant time. If an analogue signal. current input is coupled to an input of the current mirror arrangement of either of the known converter arrangements and, moreover, a forward bias current is applied to an input of the relevant current mirror arrangement, then the current mirror arrangement can be made to operate with analogue input signal currents of either polarity. However, the converter output current will still always have the same polarity, regardless of the polarity of the input signal current. Addition of a fixed opposing bias current to the converter output current will not solve this problem because, although it makes possible the production of resulting output currents of either polarity, these polarities can only be correctly governed by those of the input signal current for one specific value of the converter digital input signal.
In order to provide a solution to this problem in the case of generalized multiplying digital-to-analogue converters JP-A-60-241307 discloses a converter arrangement which includes two mutually identical complete multiplying digital-to-analogue converters. Both converters are fed with the same digital input signal at all times, i.e. their digital signal inputs are connected in parallel. The analogue input of the first converter is fed with both an analogue input signal current and a bias current as postulated above, whereas the analogne input of the second converter is fed only with a bias current which is identical to that fed to the analogne input of the first converter. The analogue output current of the second converter is sign-reversed and the result is added as a bias to the analogue output current of the first converter. Thus the biassing of the output current of the first converter is adjusted in accordance with the value of the digital input signal to the arrangement in such a way that the resulting output current (which constitutes the arrangement output) always has the correct sign relationship to the sign of the analogue input signal current to the arrangement. The effect on the output current of the first converter of the biassing of its input current is always exactly cancelled by the addition thereto of the sign-reversed output current of the second converter, regardless of the value of the digital input signal of the arrangement.
The use of two complete multiplying digital-to-analogue converters in the arrangement of JP-A-60-241307 can be rather costly, and it is an object of the present invention to provide an arrangement which can give equivalent results with less complex circuitry.